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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-05 11:11:53 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-05 11:11:53 -0800 |
| commit | 864bff14f11fc67bac40f77e5bf17c7fc61ad9f6 (patch) | |
| tree | 17469a61dc43464cd8281cc046a8c9df3702d0a1 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 0d248dd7bae707505071b309b55bac75facccab8 (diff) | |
| download | yosys-864bff14f11fc67bac40f77e5bf17c7fc61ad9f6.tar.gz yosys-864bff14f11fc67bac40f77e5bf17c7fc61ad9f6.tar.bz2 yosys-864bff14f11fc67bac40f77e5bf17c7fc61ad9f6.zip | |
Revert "Special abc9_clock wire to contain only clock signal"
This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
0 files changed, 0 insertions, 0 deletions