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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:15:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:15:13 -0700 |
| commit | 8b6085254a962da46d46724f2333abd076d32928 (patch) | |
| tree | f2dbe0f425ab5d24ba51a5e62af14b664ed16384 /techlibs/xilinx/synth_xilinx.cc | |
| parent | ff0912c75e2b15c02c9512466179e4b2a15eb3d1 (diff) | |
| download | yosys-8b6085254a962da46d46724f2333abd076d32928.tar.gz yosys-8b6085254a962da46d46724f2333abd076d32928.tar.bz2 yosys-8b6085254a962da46d46724f2333abd076d32928.zip | |
Resolve @daveshah1 comment, update synth_xilinx help
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 99c2be420..abc164533 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,13 +110,14 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); - log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); @@ -260,6 +261,7 @@ struct SynthXilinxPass : public Pass } else { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); |