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| author | David Shah <dave@ds0.me> | 2019-07-16 16:46:41 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-16 16:47:53 +0100 |
| commit | 95c8d27b0bfdea330a62a18825dea3691b4affe2 (patch) | |
| tree | 930265835858e9f5068b0c50766b6f6e4d855237 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 8da4c1ad8262216c5204c735f5297da33fed01fa (diff) | |
| download | yosys-95c8d27b0bfdea330a62a18825dea3691b4affe2.tar.gz yosys-95c8d27b0bfdea330a62a18825dea3691b4affe2.tar.bz2 yosys-95c8d27b0bfdea330a62a18825dea3691b4affe2.zip | |
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 01e75b50e..5bfbd1583 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); + // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply + // Due to current limitations of mul2dsp, we are actually mapping as a 24x17 + // unsigned multiply with MSBs set to 1'b0 + if (!nodsp || help_mode) - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18"); run("alumacc"); run("share"); |