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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:16:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:16:59 -0700 |
| commit | ae95aba60a573bf34034d6a70931bd55490d3f14 (patch) | |
| tree | edeb593904177749d70a910291712d5b06f3ca3d /techlibs/xilinx/synth_xilinx.cc | |
| parent | d99422411f568d6d8d7de7d11346718e70012df4 (diff) | |
| download | yosys-ae95aba60a573bf34034d6a70931bd55490d3f14.tar.gz yosys-ae95aba60a573bf34034d6a70931bd55490d3f14.tar.bz2 yosys-ae95aba60a573bf34034d6a70931bd55490d3f14.zip | |
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Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4f02a47ea..f59c0c622 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -269,8 +269,15 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); if (!nosrl) { + // shregmap operates on bit-level flops, not word-level, + // so break those down here Pass::call(design, "simplemap t:$dff t:$dffe"); + // shregmap -tech xilinx can cope with $shiftx and $mux + // cells for identifiying variable-length shift registers, + // so attempt to convert $pmux-es to the former Pass::call(design, "pmux2shiftx"); + // pmux2shiftx can leave behind a $pmux with a single entry + // -- need this to clean that up Pass::call(design, "opt_expr -mux_undef"); Pass::call(design, "shregmap -tech xilinx -minlen 3"); } |