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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:47:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 19:47:11 -0700 |
| commit | c26c5563845d81048dea35c4aef5f4678e177b23 (patch) | |
| tree | 966210f9e81cad2fd9180a9123e073bd55a17521 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 6b1b03d9f771addbd54358299faad181b589c9f8 (diff) | |
| download | yosys-c26c5563845d81048dea35c4aef5f4678e177b23.tar.gz yosys-c26c5563845d81048dea35c4aef5f4678e177b23.tar.bz2 yosys-c26c5563845d81048dea35c4aef5f4678e177b23.zip | |
xilinx to use abc_map.v with -max_iter 1
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b9c4df82f..263788fec 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -391,7 +391,7 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n"); run("read_verilog -icells -lib +/xilinx/abc_model.v"); - run("techmap -map +/xilinx/abc_map.v"); + run("techmap -map +/xilinx/abc_map.v -max_iter 1"); if (nowidelut) run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY)); else |