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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 09:31:24 -0800 |
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| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 09:31:24 -0800 |
| commit | c29f0c5048fce87258eb4a4b204b6584efe0170c (patch) | |
| tree | 00a301b8ebcc5156216d901affc22bab096a12be /techlibs/xilinx/synth_xilinx.cc | |
| parent | c258b99040c8414952a3aceae874dc47563540dc (diff) | |
| download | yosys-c29f0c5048fce87258eb4a4b204b6584efe0170c.tar.gz yosys-c29f0c5048fce87258eb4a4b204b6584efe0170c.tar.bz2 yosys-c29f0c5048fce87258eb4a4b204b6584efe0170c.zip | |
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
0 files changed, 0 insertions, 0 deletions