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authorEddie Hung <eddie@fpgeh.com>2019-06-06 15:31:18 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-06 15:31:18 -0700
commitd3b7ae218bd7641a40adfba7809cf0f8bdff31e6 (patch)
tree3f3e842522a3dac7b4cea628c86e5c218668f8ee /techlibs/xilinx/synth_xilinx.cc
parenta8c49168fb1e5e665e126c65dc454183a6d7826b (diff)
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Fix muxcover and its techmapping
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a70bb23f1..a0c2c781d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_cells")) {
if (!nomux || help_mode)
- run("muxcover", "(skip if '-nomux')");
+ run("muxcover -mux8 -mux16", "(skip if '-nomux')");
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");