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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 12:21:33 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-19 12:21:33 -0500 |
| commit | d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c (patch) | |
| tree | 29413acb3d172859516920d054bfddcdf0fec482 /techlibs/xilinx/synth_xilinx.cc | |
| parent | d675f22f4e4166ef2cd13f1a9a28f8bd35511539 (diff) | |
| parent | 1ac1697e15ff72e69f4dfbf6922f0871c81bdff2 (diff) | |
| download | yosys-d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c.tar.gz yosys-d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c.tar.bz2 yosys-d406f2ffd776e4f69c86a96db8e69a9aa8a1dc1c.zip | |
Merge pull request #1569 from YosysHQ/eddie/fix_1531
verilog: preserve size of $genval$-s in for loops
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
0 files changed, 0 insertions, 0 deletions