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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 09:38:42 -0700 |
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| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 09:38:42 -0700 |
| commit | e7ef7fa443c0b7c7ec9e4bbb15893053aed8c3ce (patch) | |
| tree | 95ba99bf3ce2cab5951e5bebf211249252fbf859 /techlibs/xilinx/synth_xilinx.cc | |
| parent | af5706c2a38c010e6c7343aeb1c5d6e26a6b7799 (diff) | |
| download | yosys-e7ef7fa443c0b7c7ec9e4bbb15893053aed8c3ce.tar.gz yosys-e7ef7fa443c0b7c7ec9e4bbb15893053aed8c3ce.tar.bz2 yosys-e7ef7fa443c0b7c7ec9e4bbb15893053aed8c3ce.zip | |
Reverse bits in INIT parameter for Xilinx, since MSB is shifted first
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
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