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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2018-12-18 14:08:20 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-12-18 14:08:20 -0800 |
| commit | f4d500f98e0e298a98099ec2177b43571e9cda61 (patch) | |
| tree | e39952065ae50763d5ef47ec1495ad234eaca59e /techlibs/xilinx/synth_xilinx.cc | |
| parent | 3bb9288d65f547085b79fbaffb7046f336ff7f59 (diff) | |
| parent | 2d73e1b60a43f2a621b387768134b83054f59e89 (diff) | |
| download | yosys-f4d500f98e0e298a98099ec2177b43571e9cda61.tar.gz yosys-f4d500f98e0e298a98099ec2177b43571e9cda61.tar.bz2 yosys-f4d500f98e0e298a98099ec2177b43571e9cda61.zip | |
Merge remote-tracking branch 'upstream/master'
# Conflicts:
# CHANGELOG
# frontends/verific/verific.cc
# frontends/verilog/verilog_parser.y
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 590fe61d2..b27c08529 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); if (vpr) - Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v"); - else - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut2lut.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); } |