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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:29:30 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:29:30 -0700 |
commit | f9433cc34bd52d4807c318a6b26f63cdd15d35c0 (patch) | |
tree | 0760c90dd986caddf53f55a4b372e18337364f47 /techlibs/xilinx/synth_xilinx.cc | |
parent | 99267f660f5aca3d84d885a27aad54ae3e4e8044 (diff) | |
download | yosys-f9433cc34bd52d4807c318a6b26f63cdd15d35c0.tar.gz yosys-f9433cc34bd52d4807c318a6b26f63cdd15d35c0.tar.bz2 yosys-f9433cc34bd52d4807c318a6b26f63cdd15d35c0.zip |
Remove abc_flop{,_d} attributes from ice40/cells_sim.v
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
0 files changed, 0 insertions, 0 deletions