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author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 14:21:00 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 14:21:00 -0700 |
commit | fb09c6219b057100d2e43028ec710888c20924fd (patch) | |
tree | 7f1de06040bf3276fb414acf68a12eac1421389d /techlibs/xilinx/synth_xilinx.cc | |
parent | 283e33ba5aad3a66bd14c30e1f52361c5f4c9789 (diff) | |
parent | c907899422884d959632ed42c6589a0720b681e4 (diff) | |
download | yosys-fb09c6219b057100d2e43028ec710888c20924fd.tar.gz yosys-fb09c6219b057100d2e43028ec710888c20924fd.tar.bz2 yosys-fb09c6219b057100d2e43028ec710888c20924fd.zip |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a1c4acf7e..e9a3b53a0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -42,6 +42,10 @@ struct SynthXilinxPass : public ScriptPass log(" -top <module>\n"); log(" use the specified module as top module\n"); log("\n"); + log(" -arch {xcup|xcu|xc7|xc6s}\n"); + log(" run synthesis for the specified Xilinx architecture\n"); + log(" default: xc7\n"); + log("\n"); log(" -edif <file>\n"); log(" write the design to the specified edif file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -89,7 +93,7 @@ struct SynthXilinxPass : public ScriptPass log("\n"); } - std::string top_opt, edif_file, blif_file, abc; + std::string top_opt, edif_file, blif_file, abc, arch; bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux; void clear_flags() YS_OVERRIDE @@ -101,10 +105,12 @@ struct SynthXilinxPass : public ScriptPass flatten = false; retime = false; vpr = false; + nocarry = false; nobram = false; nodram = false; nosrl = false; nomux = false; + arch = "xc7"; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -119,6 +125,10 @@ struct SynthXilinxPass : public ScriptPass top_opt = "-top " + args[++argidx]; continue; } + if (args[argidx] == "-arch" && argidx+1 < args.size()) { + arch = args[++argidx]; + continue; + } if (args[argidx] == "-edif" && argidx+1 < args.size()) { edif_file = args[++argidx]; continue; @@ -175,6 +185,9 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); + if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s") + log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str()); + if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -291,7 +304,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("check")) { run("hierarchy -check"); - run("stat"); + run("stat -tech xilinx"); run("check -noinit"); } |