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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 14:32:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-09 14:32:39 -0700 |
| commit | fd88ab5c834a45f4828a03fe7722b321e5f7c032 (patch) | |
| tree | 5d7ad50c2800bf85bad4fc8a4db9ad49ade5c39d /techlibs/xilinx/synth_xilinx.cc | |
| parent | b9e19071b8596b8d06b99cbb653325c0c9dc330f (diff) | |
| download | yosys-fd88ab5c834a45f4828a03fe7722b321e5f7c032.tar.gz yosys-fd88ab5c834a45f4828a03fe7722b321e5f7c032.tar.bz2 yosys-fd88ab5c834a45f4828a03fe7722b321e5f7c032.zip | |
synth_xilinx to call abc with -lut +/xilinx/cells.lut
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index eb37feb83..e2a2dfeeb 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -276,9 +276,9 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { if (abc == "abc9") - Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else - Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } |