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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-18 19:05:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-18 19:05:29 +0100 |
| commit | 8d295730e568421d3dc5b0779bd90d826e874254 (patch) | |
| tree | ca5acff688717ec467e1988f9327aa795f84515b /techlibs/xilinx/tests/bram1.sh | |
| parent | 694cc01f1de8e0d7db7c5e03cb93796430c6ca5b (diff) | |
| download | yosys-8d295730e568421d3dc5b0779bd90d826e874254.tar.gz yosys-8d295730e568421d3dc5b0779bd90d826e874254.tar.bz2 yosys-8d295730e568421d3dc5b0779bd90d826e874254.zip | |
Refactoring of memory_bram and xilinx brams
Diffstat (limited to 'techlibs/xilinx/tests/bram1.sh')
| -rw-r--r-- | techlibs/xilinx/tests/bram1.sh | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh index 15c4034aa..05c8ad794 100644 --- a/techlibs/xilinx/tests/bram1.sh +++ b/techlibs/xilinx/tests/bram1.sh @@ -2,15 +2,19 @@ set -e +transp_list="0 1" +abits_list="1 2 4 8 10 16 20" +dbits_list="1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80" + use_xsim=false unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims echo "all: all_list" > bram1.mk all_list="" -for transp in 0 1; do -for abits in 1 2 4 8 10 16 20; do -for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do +for transp in $transp_list; do +for abits in $abits_list; do +for dbits in $dbits_list; do if [ $(( (1 << $abits) * $dbits )) -gt 1000000 ]; then continue; fi id=`printf "%d%02d%02d" $transp $abits $dbits` echo "Creating bram1_$id.." |