diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-04-06 17:07:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-06 17:07:10 +0200 |
| commit | 8520b7fbe0b24dda47749aa870881b6b03480d4a (patch) | |
| tree | bd26ef8c9adc39cb296f04614b3c4fb33714ed13 /techlibs/xilinx/tests/bram1_tb.v | |
| parent | 169d1c471165f77612d049478ca25720071272c4 (diff) | |
| download | yosys-8520b7fbe0b24dda47749aa870881b6b03480d4a.tar.gz yosys-8520b7fbe0b24dda47749aa870881b6b03480d4a.tar.bz2 yosys-8520b7fbe0b24dda47749aa870881b6b03480d4a.zip | |
Added support for initialized xilinx brams
Diffstat (limited to 'techlibs/xilinx/tests/bram1_tb.v')
| -rw-r--r-- | techlibs/xilinx/tests/bram1_tb.v | 52 |
1 files changed, 42 insertions, 10 deletions
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v index 8f854b749..e75dfe31d 100644 --- a/techlibs/xilinx/tests/bram1_tb.v +++ b/techlibs/xilinx/tests/bram1_tb.v @@ -8,6 +8,16 @@ module bram1_tb #( reg [ABITS-1:0] RD_ADDR; wire [DBITS-1:0] RD_DATA; + localparam [ABITS-1:0] INIT_ADDR_0 = 1234; + localparam [ABITS-1:0] INIT_ADDR_1 = 4321; + localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1; + localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2; + + localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49; + localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e; + localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b; + localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46; + bram1 #( // .ABITS(ABITS), // .DBITS(DBITS), @@ -68,6 +78,11 @@ module bram1_tb #( // $dumpfile("testbench.vcd"); // $dumpvars(0, bram1_tb); + memory[INIT_ADDR_0] = INIT_DATA_0; + memory[INIT_ADDR_1] = INIT_DATA_1; + memory[INIT_ADDR_2] = INIT_DATA_2; + memory[INIT_ADDR_3] = INIT_DATA_3; + xorshift64_next; xorshift64_next; xorshift64_next; @@ -84,16 +99,33 @@ module bram1_tb #( clk <= 0; for (i = 0; i < 512; i = i+1) begin - if (DBITS > 64) - WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state; - else - WR_DATA <= xorshift64_state; - xorshift64_next; - WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); - xorshift64_next; - RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); - WR_EN <= xorshift64_state[55]; - xorshift64_next; + if (i == 0) begin + WR_EN <= 0; + RD_ADDR <= INIT_ADDR_0; + end else + if (i == 1) begin + WR_EN <= 0; + RD_ADDR <= INIT_ADDR_1; + end else + if (i == 2) begin + WR_EN <= 0; + RD_ADDR <= INIT_ADDR_2; + end else + if (i == 3) begin + WR_EN <= 0; + RD_ADDR <= INIT_ADDR_3; + end else begin + if (DBITS > 64) + WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state; + else + WR_DATA <= xorshift64_state; + xorshift64_next; + WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); + xorshift64_next; + RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); + WR_EN <= xorshift64_state[55]; + xorshift64_next; + end #1; clk <= 1; #1; clk <= 0; |