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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 13:33:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 13:33:51 +0100 |
| commit | 9c7f47bbd5fc190578054a6d018760c2f2b62c03 (patch) | |
| tree | 2349200118a55b18778b04aa858e9a2e33397767 /techlibs/xilinx/tests/bram1_tb.v | |
| parent | 462b22f44fae71767991bd4eb502d009149b3995 (diff) | |
| download | yosys-9c7f47bbd5fc190578054a6d018760c2f2b62c03.tar.gz yosys-9c7f47bbd5fc190578054a6d018760c2f2b62c03.tar.bz2 yosys-9c7f47bbd5fc190578054a6d018760c2f2b62c03.zip | |
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx/tests/bram1_tb.v')
| -rw-r--r-- | techlibs/xilinx/tests/bram1_tb.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v index 98e6bafe6..c14cf6e30 100644 --- a/techlibs/xilinx/tests/bram1_tb.v +++ b/techlibs/xilinx/tests/bram1_tb.v @@ -40,10 +40,13 @@ module bram1_tb #( reg [DBITS-1:0] memory [0:2**ABITS-1]; reg [DBITS-1:0] expected_rd; + event error; + reg error_ind = 0; + integer i, j; initial begin - $dumpfile("testbench.vcd"); - $dumpvars(0, bram1_tb); + // $dumpfile("testbench.vcd"); + // $dumpvars(0, bram1_tb); clk <= 0; for (i = 0; i < 256; i = i+1) begin WR_DATA <= i; @@ -68,6 +71,7 @@ module bram1_tb #( end $display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR"); + if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end end end endmodule |