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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-11-21 13:05:30 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-01-29 01:40:00 +0100 |
| commit | 7e0e42f907260e76e3c7cb01c907a0cf61a6e326 (patch) | |
| tree | 1a948b1efc41c7d639feff064eb9e8713c2486eb /techlibs/xilinx/tests/test_dsp48_model.sh | |
| parent | 7939727d14f44b5d56ca3806d0907e9fceea2882 (diff) | |
| download | yosys-7e0e42f907260e76e3c7cb01c907a0cf61a6e326.tar.gz yosys-7e0e42f907260e76e3c7cb01c907a0cf61a6e326.tar.bz2 yosys-7e0e42f907260e76e3c7cb01c907a0cf61a6e326.zip | |
xilinx: Add simulation model for DSP48 (Virtex 4).
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp48_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp48_model.sh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/test_dsp48_model.sh b/techlibs/xilinx/tests/test_dsp48_model.sh new file mode 100644 index 000000000..9a73f9b0c --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48_model.sh @@ -0,0 +1,14 @@ +#!/bin/bash +set -ex +if [ -z $ISE_DIR ]; then + ISE_DIR=/opt/Xilinx/ISE/14.7 +fi +sed 's/DSP48 /DSP48_UUT /; /DSP48_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48_model_uut.v +if [ ! -f "test_dsp48_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48.v test_dsp48_model_ref.v +fi +for tb in mult_allreg mult_noreg mult_inreg +do + iverilog -s $tb -s glbl -o test_dsp48_model test_dsp48_model.v test_dsp48_model_uut.v test_dsp48_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v + vvp -N ./test_dsp48_model +done |