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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:31:42 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:31:42 -0800 |
| commit | 405e974fe51f4ede0b374ddddc398a26e04b0265 (patch) | |
| tree | 61f646fe54f9f57d18236058aca8746d8603eed8 /techlibs/xilinx/tests/test_dsp48a1_model.sh | |
| parent | ece423415cbc17654c6ac81a0f4b15783c558660 (diff) | |
| parent | c0a17c2457532726b05586d3b7a030bd9f372dea (diff) | |
| download | yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.tar.gz yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.tar.bz2 yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp48a1_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp48a1_model.sh | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/test_dsp48a1_model.sh b/techlibs/xilinx/tests/test_dsp48a1_model.sh new file mode 100644 index 000000000..a14a78e72 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48a1_model.sh @@ -0,0 +1,17 @@ +#!/bin/bash +set -ex +if [ -z $ISE_DIR ]; then + ISE_DIR=/opt/Xilinx/ISE/14.7 +fi +sed 's/DSP48A1/MARKER1/; s/DSP48A/DSP48A_UUT/; s/MARKER1/DSP48A1_UUT/; /module DSP48A_UUT/,/endmodule/ p; /module DSP48A1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48a1_model_uut.v +if [ ! -f "test_dsp48a1_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v test_dsp48a1_model_ref.v +fi +if [ ! -f "test_dsp48a_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A.v test_dsp48a_model_ref.v +fi +for tb in mult_allreg mult_noreg mult_inreg +do + iverilog -s $tb -s glbl -o test_dsp48a1_model test_dsp48a1_model.v test_dsp48a1_model_uut.v test_dsp48a1_model_ref.v test_dsp48a_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v + vvp -N ./test_dsp48a1_model +done |