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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-22 14:30:04 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-23 20:36:43 +0100 |
| commit | dadaf7ed788370c94a463e5e479bed4d540cdf4b (patch) | |
| tree | 3b7ce98de86ecc5a7a0758a784ff81c6f8f94322 /techlibs/xilinx/tests/test_dsp48a1_model.sh | |
| parent | aa1adb0f1e43c353356a8283ad1f2fc007d9f54b (diff) | |
| download | yosys-dadaf7ed788370c94a463e5e479bed4d540cdf4b.tar.gz yosys-dadaf7ed788370c94a463e5e479bed4d540cdf4b.tar.bz2 yosys-dadaf7ed788370c94a463e5e479bed4d540cdf4b.zip | |
xilinx: Test our DSP48A/DSP48A1 simulation models.
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp48a1_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp48a1_model.sh | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/test_dsp48a1_model.sh b/techlibs/xilinx/tests/test_dsp48a1_model.sh new file mode 100644 index 000000000..a14a78e72 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp48a1_model.sh @@ -0,0 +1,17 @@ +#!/bin/bash +set -ex +if [ -z $ISE_DIR ]; then + ISE_DIR=/opt/Xilinx/ISE/14.7 +fi +sed 's/DSP48A1/MARKER1/; s/DSP48A/DSP48A_UUT/; s/MARKER1/DSP48A1_UUT/; /module DSP48A_UUT/,/endmodule/ p; /module DSP48A1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp48a1_model_uut.v +if [ ! -f "test_dsp48a1_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v test_dsp48a1_model_ref.v +fi +if [ ! -f "test_dsp48a_model_ref.v" ]; then + cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A.v test_dsp48a_model_ref.v +fi +for tb in mult_allreg mult_noreg mult_inreg +do + iverilog -s $tb -s glbl -o test_dsp48a1_model test_dsp48a1_model.v test_dsp48a1_model_uut.v test_dsp48a1_model_ref.v test_dsp48a_model_ref.v $ISE_DIR/ISE_DS/ISE/verilog/src/glbl.v + vvp -N ./test_dsp48a1_model +done |