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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 19:39:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 19:39:12 -0700 |
| commit | 1123c09588a6dd3964605de229c6bc4ac158b50e (patch) | |
| tree | 6f6b950cfc30c4db0963a90fe065964489fa292b /techlibs/xilinx/tests/test_dsp_model.sh | |
| parent | 18ebb86edbade4a94833dead59d69fddd980f5bd (diff) | |
| parent | d5f0794a531b36976d2c4d181b1c3921b801bbfa (diff) | |
| download | yosys-1123c09588a6dd3964605de229c6bc4ac158b50e.tar.gz yosys-1123c09588a6dd3964605de229c6bc4ac158b50e.tar.bz2 yosys-1123c09588a6dd3964605de229c6bc4ac158b50e.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.sh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh new file mode 100644 index 000000000..ae925c402 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -0,0 +1,14 @@ +#!/bin/bash +set -ex +sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +if [ ! -f "test_dsp_model_ref.v" ]; then + cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v +fi +for tb in macc_overflow_underflow \ + simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ + mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc +do + iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v + vvp -N ./test_dsp_model +done |