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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 11:26:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-29 11:26:22 -0700 |
| commit | 8474c5b366660153cae03a9de4af8e1ed809856d (patch) | |
| tree | cd157ab16b528565ced19f422ffece1c6110f53e /techlibs/xilinx/tests/test_dsp_model.sh | |
| parent | ce0631c371f69f0132ea9ee4bc8f5ee576dbb1a3 (diff) | |
| parent | b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 (diff) | |
| download | yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.gz yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.bz2 yosys-8474c5b366660153cae03a9de4af8e1ed809856d.zip | |
Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.sh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh new file mode 100644 index 000000000..ae925c402 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -0,0 +1,14 @@ +#!/bin/bash +set -ex +sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +if [ ! -f "test_dsp_model_ref.v" ]; then + cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v +fi +for tb in macc_overflow_underflow \ + simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ + mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc +do + iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v + vvp -N ./test_dsp_model +done |