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| author | David Shah <dave@ds0.me> | 2019-08-08 11:39:35 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:39:35 +0100 |
| commit | b8cd4ad64ae9a45faecffc1a6b92a8219755bc60 (patch) | |
| tree | 14ef43619585b04e7c86c4c698fb089ea2252181 /techlibs/xilinx/tests/test_dsp_model.sh | |
| parent | 57aeb4cc01058c0167e5a4eda9def97b0bb1741b (diff) | |
| download | yosys-b8cd4ad64ae9a45faecffc1a6b92a8219755bc60.tar.gz yosys-b8cd4ad64ae9a45faecffc1a6b92a8219755bc60.tar.bz2 yosys-b8cd4ad64ae9a45faecffc1a6b92a8219755bc60.zip | |
DSP48E1 sim model: add SIMD tests
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.sh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 337530e87..2acd97eb4 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,8 +4,10 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ - mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc +for tb in simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ + mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc \ + do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model |