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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-10-01 11:04:32 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-01 11:04:32 +0300 |
| commit | e092c4ae6b60cf67efd16efbfbf739895ad501c0 (patch) | |
| tree | 939a5b94d14a11df511aa95482458b33a1f6139f /techlibs/xilinx/tests/test_dsp_model.sh | |
| parent | 1070f2e90b9ba37856932189ef09a0f2316d9a21 (diff) | |
| parent | d963e8c2c6207ad98d48dc528922ad58c030173f (diff) | |
| download | yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.gz yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.tar.bz2 yosys-e092c4ae6b60cf67efd16efbfbf739895ad501c0.zip | |
Merge branch 'master' into SergeyDegtyar/efinix
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.sh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh new file mode 100644 index 000000000..ae925c402 --- /dev/null +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -0,0 +1,14 @@ +#!/bin/bash +set -ex +sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +if [ ! -f "test_dsp_model_ref.v" ]; then + cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v +fi +for tb in macc_overflow_underflow \ + simd24_preadd_noreg_nocasc simd12_preadd_noreg_nocasc \ + mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc mult_inreg_preadd_nocasc +do + iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v + vvp -N ./test_dsp_model +done |