[wip] sim model testing

Signed-off-by: David Shah <dave@ds0.me>

1 files changed, 11 insertions, 0 deletions

diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh
new file mode 100644
index 000000000..5455294da
--- /dev/null
+++ b/techlibs/xilinx/tests/test_dsp_model.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+set -ex
+sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
+if [ ! -f "test_dsp_model_ref.v" ]; then
+	cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
+fi
+for tb in mult_noreg_nopreadd_nocasc
+do
+	iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
+	vvp -N ./test_dsp_model
+done