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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-23 08:36:20 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-23 08:36:20 -0800 |
| commit | 509070f82fa458ccc8515eb4b09f1e4ab7068110 (patch) | |
| tree | 4fe7047d3f573fa37dd858e1b2b56963c061e4bf /techlibs/xilinx/tests | |
| parent | 6eadd4390a3c9650912bac9fbf8bd309f0088217 (diff) | |
| download | yosys-509070f82fa458ccc8515eb4b09f1e4ab7068110.tar.gz yosys-509070f82fa458ccc8515eb4b09f1e4ab7068110.tar.bz2 yosys-509070f82fa458ccc8515eb4b09f1e4ab7068110.zip | |
Disable clock domain partitioning in Yosys pass, let ABC do it
Diffstat (limited to 'techlibs/xilinx/tests')
0 files changed, 0 insertions, 0 deletions