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| author | David Shah <dave@ds0.me> | 2019-08-08 11:32:43 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:32:43 +0100 |
| commit | 57aeb4cc01058c0167e5a4eda9def97b0bb1741b (patch) | |
| tree | e21f3f0d1723188bababc3bca3f02199effe7784 /techlibs/xilinx/tests | |
| parent | d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5 (diff) | |
| download | yosys-57aeb4cc01058c0167e5a4eda9def97b0bb1741b.tar.gz yosys-57aeb4cc01058c0167e5a4eda9def97b0bb1741b.tar.bz2 yosys-57aeb4cc01058c0167e5a4eda9def97b0bb1741b.zip | |
DSP48E1 model: test CE inputs
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/tests')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.v | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index 6f1ca045a..7086634d2 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -134,7 +134,7 @@ module testbench; end {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = 0; - repeat (5000) begin + repeat (10000) begin clkcycle; config_valid = 0; while (!config_valid) begin @@ -146,6 +146,13 @@ module testbench; D = $urandom; PCIN = {$urandom, $urandom}; + {CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = $urandom | $urandom | $urandom; + {CED, CEINMODE, CEM, CEP} = $urandom | $urandom | $urandom | $urandom; + + // Otherwise we can accidentally create illegal configs + CEINMODE = CECTRL; + CEALUMODE = CECTRL; + {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; {ALUMODE, INMODE} = $urandom; CARRYINSEL = $urandom & $urandom & $urandom; @@ -162,7 +169,7 @@ module testbench; if (CARRYINSEL == 3'b101) OPMODE = 7'b0011010; if (CARRYINSEL == 3'b110) OPMODE = 7'b0010101; if (CARRYINSEL == 3'b111) OPMODE = 7'b0100011; - + drc; end end |