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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:31:42 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 14:31:42 -0800 |
| commit | 405e974fe51f4ede0b374ddddc398a26e04b0265 (patch) | |
| tree | 61f646fe54f9f57d18236058aca8746d8603eed8 /techlibs/xilinx/xc3sda_dsp_map.v | |
| parent | ece423415cbc17654c6ac81a0f4b15783c558660 (diff) | |
| parent | c0a17c2457532726b05586d3b7a030bd9f372dea (diff) | |
| download | yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.tar.gz yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.tar.bz2 yosys-405e974fe51f4ede0b374ddddc398a26e04b0265.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/xc3sda_dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/xc3sda_dsp_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v index 87348a173..258f90395 100644 --- a/techlibs/xilinx/xc3sda_dsp_map.v +++ b/techlibs/xilinx/xc3sda_dsp_map.v @@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D(18'b0), .P(P_48), - .OPMODE(8'b0000010) + .OPMODE(8'b0000001) ); assign Y = P_48; endmodule |