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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-11 17:08:40 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-11 17:08:40 +0100 |
| commit | ec3faa7b967564dabdd465267657def86846b259 (patch) | |
| tree | a0e6b31ff0fb94e54260a078900144a30b20804f /techlibs/xilinx/xc3sda_dsp_map.v | |
| parent | 0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1 (diff) | |
| parent | 1d148491c5a9b816297c08e5ea3a98ff0bd3623d (diff) | |
| download | yosys-ec3faa7b967564dabdd465267657def86846b259.tar.gz yosys-ec3faa7b967564dabdd465267657def86846b259.tar.bz2 yosys-ec3faa7b967564dabdd465267657def86846b259.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'techlibs/xilinx/xc3sda_dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/xc3sda_dsp_map.v | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v new file mode 100644 index 000000000..87348a173 --- /dev/null +++ b/techlibs/xilinx/xc3sda_dsp_map.v @@ -0,0 +1,34 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48A #( + // Disable all registers + .A0REG(0), + .A1REG(0), + .B0REG(0), + .B1REG(0), + .CARRYINREG(0), + .CARRYINSEL("OPMODE5"), + .CREG(0), + .DREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A(A), + .B(B), + .C(48'b0), + .D(18'b0), + .P(P_48), + + .OPMODE(8'b0000010) + ); + assign Y = P_48; +endmodule + |