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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-10-08 17:00:30 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-10-22 18:06:57 +0200 |
| commit | 7b350cacd410b16fdac5a6933aea1bb009b83621 (patch) | |
| tree | 934e58717f9ba5463d97d56eaf8c82d875677494 /techlibs/xilinx/xc4v_dsp_map.v | |
| parent | a3a7bb9bf7160d434db7a4737e68f6b015b221ef (diff) | |
| download | yosys-7b350cacd410b16fdac5a6933aea1bb009b83621.tar.gz yosys-7b350cacd410b16fdac5a6933aea1bb009b83621.tar.bz2 yosys-7b350cacd410b16fdac5a6933aea1bb009b83621.zip | |
xilinx: Support multiplier mapping for all families.
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
Diffstat (limited to 'techlibs/xilinx/xc4v_dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/xc4v_dsp_map.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc4v_dsp_map.v b/techlibs/xilinx/xc4v_dsp_map.v new file mode 100644 index 000000000..69c42f343 --- /dev/null +++ b/techlibs/xilinx/xc4v_dsp_map.v @@ -0,0 +1,38 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48 #( + // Disable all registers + .AREG(0), + .BREG(0), + .B_INPUT("DIRECT"), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .SUBTRACTREG(0), + .LEGACY_MODE("MULT18X18") + ) _TECHMAP_REPLACE_ ( + //Data path + .A(A), + .B(B), + .C(48'b0), + .P(P_48), + + .SUBTRACT(1'b0), + .OPMODE(7'b000101), + .CARRYINSEL(2'b00), + + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule |