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| author | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-30 13:57:15 +0100 |
| commit | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch) | |
| tree | 4780799b6c1dc1d150b80aa142e6c53e06760cb3 /techlibs/xilinx/xc6s_brams_bb.v | |
| parent | edff79a25a802e5b1816608b48e3ac335ad87147 (diff) | |
| parent | 694e30a35426b9582a1f2db730528d4d34305795 (diff) | |
| download | yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.gz yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.tar.bz2 yosys-6919c0f9b010c94a0a1a31cd788301e78a1bcbfb.zip | |
Merge branch 'master' into xc7dsp
Diffstat (limited to 'techlibs/xilinx/xc6s_brams_bb.v')
| -rw-r--r-- | techlibs/xilinx/xc6s_brams_bb.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v index eb1a29579..041d6b54f 100644 --- a/techlibs/xilinx/xc6s_brams_bb.v +++ b/techlibs/xilinx/xc6s_brams_bb.v @@ -1,5 +1,7 @@ module RAMB8BWER ( + (* clkbuf_sink *) input CLKAWRCLK, + (* clkbuf_sink *) input CLKBRDCLK, input ENAWREN, input ENBRDEN, @@ -87,7 +89,9 @@ module RAMB8BWER ( endmodule module RAMB16BWER ( + (* clkbuf_sink *) input CLKA, + (* clkbuf_sink *) input CLKB, input ENA, input ENB, |