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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:57:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:57:52 -0700 |
| commit | d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (patch) | |
| tree | aceb37b755f6b112e754bbdd50f0a4a6a6ee111d /techlibs/xilinx/xc6s_brams_map.v | |
| parent | 297a9802122817e143b1e4b87fd0d4e357606a72 (diff) | |
| parent | 3f4886e7a3ff14578b9c6d614efd360478e5886e (diff) | |
| download | yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.tar.gz yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.tar.bz2 yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.zip | |
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Diffstat (limited to 'techlibs/xilinx/xc6s_brams_map.v')
| -rw-r--r-- | techlibs/xilinx/xc6s_brams_map.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/xc6s_brams_map.v b/techlibs/xilinx/xc6s_brams_map.v index c9b33af42..16fd15e74 100644 --- a/techlibs/xilinx/xc6s_brams_map.v +++ b/techlibs/xilinx/xc6s_brams_map.v @@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK2 ^ !CLKPOL2), .ENBRDEN(A1EN), .REGCEBREGCE(|1), - .RSTB(|0) + .RSTBRST(|0) ); endmodule @@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end else begin @@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT .CLKBRDCLK(CLK3 ^ !CLKPOL3), .ENBRDEN(|1), .REGCEBREGCE(|0), - .RSTB(|0), + .RSTBRST(|0), .WEBWEU(B1EN_2) ); end endgenerate |