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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-09-23 12:41:42 +0200 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-30 12:52:43 +0200 |
| commit | 4535f2c6943107d88e9196c9705fc5d92f604f14 (patch) | |
| tree | 5139870d0a9c156a1eff6f9d370c669aa170a5b9 /techlibs/xilinx/xc6s_ff_map.v | |
| parent | d5f0794a531b36976d2c4d181b1c3921b801bbfa (diff) | |
| download | yosys-4535f2c6943107d88e9196c9705fc5d92f604f14.tar.gz yosys-4535f2c6943107d88e9196c9705fc5d92f604f14.tar.bz2 yosys-4535f2c6943107d88e9196c9705fc5d92f604f14.zip | |
synth_xilinx: Support latches, remove used-up FF init values.
Fixes #1387.
Diffstat (limited to 'techlibs/xilinx/xc6s_ff_map.v')
| -rw-r--r-- | techlibs/xilinx/xc6s_ff_map.v | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v index 520a67579..bf35b09e5 100644 --- a/techlibs/xilinx/xc6s_ff_map.v +++ b/techlibs/xilinx/xc6s_ff_map.v @@ -18,7 +18,12 @@ */ // ============================================================================ -// FF mapping +// FF mapping for Spartan 6. The primitives used are the same as Series 7, +// but with one major difference: the initial value is implied by the +// primitive type used (FFs with reset pin must have INIT set to 0 or x, FFs +// with set pin must have INIT set to 1 or x). For Yosys primitives without +// set/reset, this means we have to pick the primitive type based on the INIT +// value. `ifndef _NO_FFS @@ -29,6 +34,7 @@ module \$_DFF_N_ (input D, C, output Q); else FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_P_ (input D, C, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -37,6 +43,7 @@ module \$_DFF_P_ (input D, C, output Q); else FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_NP_ (input D, C, E, output Q); @@ -46,6 +53,7 @@ module \$_DFFE_NP_ (input D, C, E, output Q); else FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFFE_PP_ (input D, C, E, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -54,6 +62,7 @@ module \$_DFFE_PP_ (input D, C, E, output Q); else FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NN0_ (input D, C, R, output Q); @@ -63,6 +72,7 @@ module \$_DFF_NN0_ (input D, C, R, output Q); else FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NP0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -71,6 +81,7 @@ module \$_DFF_NP0_ (input D, C, R, output Q); else FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PN0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -79,6 +90,7 @@ module \$_DFF_PN0_ (input D, C, R, output Q); else FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PP0_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -87,6 +99,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); else FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NN1_ (input D, C, R, output Q); @@ -96,6 +109,7 @@ module \$_DFF_NN1_ (input D, C, R, output Q); else FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_NP1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -104,6 +118,7 @@ module \$_DFF_NP1_ (input D, C, R, output Q); else FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PN1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -112,6 +127,7 @@ module \$_DFF_PN1_ (input D, C, R, output Q); else FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule module \$_DFF_PP1_ (input D, C, R, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; @@ -120,6 +136,26 @@ module \$_DFF_PP1_ (input D, C, R, output Q); else FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +module \$_DLATCH_N_ (input E, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0)); + else + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule +module \$_DLATCH_P_ (input E, D, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0)); + else + LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule `endif |