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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 12:55:35 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-11 12:55:35 -0700 |
| commit | 19c1c3cfa351eb818065054ca6358006f38acb9c (patch) | |
| tree | 117b9185aa8de17a107d05060aef2885f9cea678 /techlibs/xilinx/xc7_brams.txt | |
| parent | 931adbaf74a2e489e1adfe202ce583e979384e55 (diff) | |
| parent | ce250b341c912a3357b13259c1b0b6ed0a7b95a6 (diff) | |
| download | yosys-19c1c3cfa351eb818065054ca6358006f38acb9c.tar.gz yosys-19c1c3cfa351eb818065054ca6358006f38acb9c.tar.bz2 yosys-19c1c3cfa351eb818065054ca6358006f38acb9c.zip | |
Merge pull request #1182 from koriakin/xc6s-bram
synth_xilinx: Initial Spartan 6 block RAM inference support.
Diffstat (limited to 'techlibs/xilinx/xc7_brams.txt')
| -rw-r--r-- | techlibs/xilinx/xc7_brams.txt | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc7_brams.txt b/techlibs/xilinx/xc7_brams.txt new file mode 100644 index 000000000..f1161114e --- /dev/null +++ b/techlibs/xilinx/xc7_brams.txt @@ -0,0 +1,105 @@ + +bram $__XILINX_RAMB36_SDP + init 1 + abits 9 + dbits 72 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 8 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB18_SDP + init 1 + abits 9 + dbits 36 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 4 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_TDP + init 1 + abits 10 @a10d36 + dbits 36 @a10d36 + abits 11 @a11d18 + dbits 18 @a11d18 + abits 12 @a12d9 + dbits 9 @a12d9 + abits 13 @a13d4 + dbits 4 @a13d4 + abits 14 @a14d2 + dbits 2 @a14d2 + abits 15 @a15d1 + dbits 1 @a15d1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 4 @a10d36 + enable 1 2 @a11d18 + enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB18_TDP + init 1 + abits 10 @a10d18 + dbits 18 @a10d18 + abits 11 @a11d9 + dbits 9 @a11d9 + abits 12 @a12d4 + dbits 4 @a12d4 + abits 13 @a13d2 + dbits 2 @a13d2 + abits 14 @a14d1 + dbits 1 @a14d1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 2 @a10d18 + enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__XILINX_RAMB36_SDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_SDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB36_TDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp +endmatch + |