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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-13 19:36:59 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-08-13 19:36:59 +0000 |
| commit | 3c75a72feb1cf83fa8fc138aa69155446b6b74f0 (patch) | |
| tree | 91be55ce3dd95199c303ef5de87df28d4d3c0e60 /techlibs/xilinx/xc7_brams_bb.v | |
| parent | 49765ec19ea63bff5f04e28e5729d5852a2f8287 (diff) | |
| download | yosys-3c75a72feb1cf83fa8fc138aa69155446b6b74f0.tar.gz yosys-3c75a72feb1cf83fa8fc138aa69155446b6b74f0.tar.bz2 yosys-3c75a72feb1cf83fa8fc138aa69155446b6b74f0.zip | |
move attributes to wires
Diffstat (limited to 'techlibs/xilinx/xc7_brams_bb.v')
| -rw-r--r-- | techlibs/xilinx/xc7_brams_bb.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index 046a8fa26..a43b4b5a1 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -1,6 +1,7 @@ -(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *) module RAMB18E1 ( + (* clkbuf_sink *) input CLKARDCLK, + (* clkbuf_sink *) input CLKBWRCLK, input ENARDEN, input ENBWREN, @@ -123,9 +124,10 @@ module RAMB18E1 ( parameter SIM_DEVICE = "VIRTEX6"; endmodule -(* clkbuf_sink = "CLKARDCLK,CLKBWRCLK" *) module RAMB36E1 ( + (* clkbuf_sink *) input CLKARDCLK, + (* clkbuf_sink *) input CLKBWRCLK, input ENARDEN, input ENBWREN, |