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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:00:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-05 12:00:23 -0700 |
| commit | 903cd58acf7c490e0b75e34742966dc62e61028f (patch) | |
| tree | 24ed0acd4627da70e762abfb362a20fa3ae64b49 /techlibs/xilinx/xc7_brams_bb.v | |
| parent | 58ec1df4c26599338f2f45941ed8ca402abfe607 (diff) | |
| parent | aa1491add3722e4cfae35755cc4cecfd3e5a6c82 (diff) | |
| download | yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.gz yosys-903cd58acf7c490e0b75e34742966dc62e61028f.tar.bz2 yosys-903cd58acf7c490e0b75e34742966dc62e61028f.zip | |
Merge pull request #1312 from YosysHQ/xaig_arrival
Allow arrival times of sequential outputs to be specified to abc9
Diffstat (limited to 'techlibs/xilinx/xc7_brams_bb.v')
| -rw-r--r-- | techlibs/xilinx/xc7_brams_bb.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index a43b4b5a1..5b40a457d 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -1,3 +1,5 @@ +// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147 + module RAMB18E1 ( (* clkbuf_sink *) input CLKARDCLK, @@ -21,9 +23,13 @@ module RAMB18E1 ( input [1:0] WEA, input [3:0] WEBWE, + (* abc_arrival=2454 *) output [15:0] DOADO, + (* abc_arrival=2454 *) output [15:0] DOBDO, + (* abc_arrival=2454 *) output [1:0] DOPADOP, + (* abc_arrival=2454 *) output [1:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -147,9 +153,13 @@ module RAMB36E1 ( input [3:0] WEA, input [7:0] WEBWE, + (* abc_arrival=2454 *) output [31:0] DOADO, + (* abc_arrival=2454 *) output [31:0] DOBDO, + (* abc_arrival=2454 *) output [3:0] DOPADOP, + (* abc_arrival=2454 *) output [3:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; |