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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-27 10:19:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-27 10:19:27 -0700 |
| commit | eab3c1432b717bb341773878bf0daece7d39dec8 (patch) | |
| tree | e30aa036be3c84d29f357e2faa015190ec8e195c /techlibs/xilinx/xc7_brams_bb.v | |
| parent | fdbcf789099d327bd5e9f2e0658cdad754b09db2 (diff) | |
| parent | 5fb4b12cb50b870b546d76f9c702678d8f0aa60a (diff) | |
| download | yosys-eab3c1432b717bb341773878bf0daece7d39dec8.tar.gz yosys-eab3c1432b717bb341773878bf0daece7d39dec8.tar.bz2 yosys-eab3c1432b717bb341773878bf0daece7d39dec8.zip | |
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
Add clock buffer insertion pass, improve iopadmap.
Diffstat (limited to 'techlibs/xilinx/xc7_brams_bb.v')
| -rw-r--r-- | techlibs/xilinx/xc7_brams_bb.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index a682ba4a7..a43b4b5a1 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -1,5 +1,7 @@ module RAMB18E1 ( + (* clkbuf_sink *) input CLKARDCLK, + (* clkbuf_sink *) input CLKBWRCLK, input ENARDEN, input ENBWREN, @@ -123,7 +125,9 @@ module RAMB18E1 ( endmodule module RAMB36E1 ( + (* clkbuf_sink *) input CLKARDCLK, + (* clkbuf_sink *) input CLKBWRCLK, input ENARDEN, input ENBWREN, |