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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-04 15:35:47 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 01:00:29 +0100 |
| commit | 30854b9c7f23e2817a445761022668d6b0f7c0ef (patch) | |
| tree | 83471ee10f31862015bab189c3684ade82e23c47 /techlibs/xilinx/xcu_brams_map.v | |
| parent | 95c46ccc555769cd9d24bae27e0b7264f06e3d66 (diff) | |
| download | yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.gz yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.tar.bz2 yosys-30854b9c7f23e2817a445761022668d6b0f7c0ef.zip | |
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
Diffstat (limited to 'techlibs/xilinx/xcu_brams_map.v')
| -rw-r--r-- | techlibs/xilinx/xcu_brams_map.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/xcu_brams_map.v b/techlibs/xilinx/xcu_brams_map.v index 6e7925b57..b6719b2dd 100644 --- a/techlibs/xilinx/xcu_brams_map.v +++ b/techlibs/xilinx/xcu_brams_map.v @@ -1,3 +1,5 @@ +// Ultrascale and Ultrascale Plus block RAM mapping. + module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; |