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| author | whitequark <whitequark@whitequark.org> | 2021-01-26 21:18:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-26 21:18:06 +0000 |
| commit | d73ffa07f2fccc0da396276955f64648becab173 (patch) | |
| tree | afc085451c54f609f59bab7b7310ab9eb0d2d785 /techlibs/xilinx/xilinx_dffopt.cc | |
| parent | 8eaeaa8434681403d12ac5d6a9761d3720b4ef98 (diff) | |
| parent | c8415884d1c2bc66479dcbce491383e1a077c5ef (diff) | |
| download | yosys-d73ffa07f2fccc0da396276955f64648becab173.tar.gz yosys-d73ffa07f2fccc0da396276955f64648becab173.tar.bz2 yosys-d73ffa07f2fccc0da396276955f64648becab173.zip | |
Merge pull request #2544 from modwizcode/fix-clock
CXXRTL: Fix sliced bits as clock inputs
Diffstat (limited to 'techlibs/xilinx/xilinx_dffopt.cc')
0 files changed, 0 insertions, 0 deletions