Added simple xilinx7 technology mapping files

1 files changed, 61 insertions, 0 deletions

diff --git a/techlibs/xilinx7/counter_tb.v b/techlibs/xilinx7/counter_tb.v
new file mode 100644
index 000000000..b6b64269e
--- /dev/null
+++ b/techlibs/xilinx7/counter_tb.v
@@ -0,0 +1,61 @@
+`timescale  1 ns / 1 ps
+
+module testbench;
+
+reg clk, en, rst;
+wire [3:0] count;
+
+counter uut_counter(
+	.clk(clk),
+	.count(count),
+	.en(en),
+	.rst(rst)
+);
+
+initial begin
+	clk <= 0;
+	forever begin
+		#50;
+		clk <= ~clk;
+	end
+end
+
+initial begin
+	@(posedge clk);
+	forever begin
+		@(posedge clk);
+		$display("%d", count);
+	end
+end
+
+initial begin
+	rst <= 1; en <= 0; @(posedge clk);
+	rst <= 1; en <= 0; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 1; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 1; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	rst <= 0; en <= 1; @(posedge clk);
+	rst <= 0; en <= 0; @(posedge clk);
+	$finish;
+end
+
+endmodule