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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 13:49:24 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-11 13:49:24 -0800 |
| commit | 04a2eb82045a658de22cea610a3ac8c5dee9333c (patch) | |
| tree | 6014022c0a9e010e0bea36eff1bd1919133e10b0 /techlibs/xilinx | |
| parent | d2df2a8fef8d01b70fa5faa4397e1d628b9ceb5b (diff) | |
| parent | 1ccee4b95e1e7a2edf55c989d6acc7d6f63762ba (diff) | |
| download | yosys-04a2eb82045a658de22cea610a3ac8c5dee9333c.tar.gz yosys-04a2eb82045a658de22cea610a3ac8c5dee9333c.tar.bz2 yosys-04a2eb82045a658de22cea610a3ac8c5dee9333c.zip | |
Merge pull request #1625 from YosysHQ/eddie/abc9_mfs
abc9: re-enable "&mfs" optimisation for synth_{xilinx,ecp5}
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 51d2cbbd2..63d00027a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -556,7 +556,6 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); - abc9_opts += " -nomfs"; if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else |