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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-26 19:06:10 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-26 19:06:10 +0200 |
| commit | 0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3 (patch) | |
| tree | 17866fa26c6bed6f106709d9a14d4f3ebb14f482 /techlibs/xilinx | |
| parent | 0b7d648c6a71594f8a17e78aef8f62b6f6448390 (diff) | |
| parent | ea0b6258ab392b6186ee5d75a75da944b25d0392 (diff) | |
| download | yosys-0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3.tar.gz yosys-0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3.tar.bz2 yosys-0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3.zip | |
Merge pull request #1137 from mmicko/cell_sim_fix
Simulation model verilog fix
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 50d588a9e..f4598dcf4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -282,7 +282,7 @@ module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; |