diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:14:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:14:11 -0700 |
| commit | 1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae (patch) | |
| tree | 7ac4ff918567ce713a9ee66ea5729cde3a2d6aca /techlibs/xilinx | |
| parent | 69863f7698853d502f6d9bf810fcfda8fce87e6e (diff) | |
| download | yosys-1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae.tar.gz yosys-1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae.tar.bz2 yosys-1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae.zip | |
Trim A_WIDTH by Y_WIDTH-1
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 38c8a49e7..60bc08b48 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -168,7 +168,7 @@ module \$shiftx (A, B, Y); end else if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); end // If the LSB of B is constant zero (and Y_WIDTH is 1) then // we can optimise by removing every other entry from A |