Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

7 files changed, 652 insertions, 204 deletions

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 319c4400a..289742808 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -29,24 +29,35 @@ module GND(output G);
   assign G = 0;
 endmodule
 
-module IBUF(output O, input I);
+module IBUF(
+    output O,
+    (* iopad_external_pin *)
+    input I);
   parameter IOSTANDARD = "default";
   parameter IBUF_LOW_PWR = 0;
   assign O = I;
 endmodule
 
-module OBUF(output O, input I);
+module OBUF(
+    (* iopad_external_pin *)
+    output O,
+    input I);
   parameter IOSTANDARD = "default";
   parameter DRIVE = 12;
   parameter SLEW = "SLOW";
   assign O = I;
 endmodule
 
-module BUFG(output O, input I);
+module BUFG(
+    (* clkbuf_driver *)
+    output O,
+    input I);
+
   assign O = I;
 endmodule
 
 module BUFGCTRL(
+    (* clkbuf_driver *)
     output O,
     input I0, input I1,
     input S0, input S1,
@@ -72,7 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
 
 endmodule
 
-module BUFHCE(output O, input I, input CE);
+module BUFHCE(
+    (* clkbuf_driver *)
+    output O,
+    input I,
+    input CE);
 
 parameter [0:0] INIT_OUT = 1'b0;
 parameter CE_TYPE = "SYNC";
@@ -183,9 +198,11 @@ endmodule
 
 (* abc_box_id = 4, lib_whitebox *)
 module CARRY4(
-  (* abc_carry *) output [3:0] CO,
+  (* abc_carry *)
+  output [3:0] CO,
   output [3:0] O,
-  (* abc_carry *) input CI,
+  (* abc_carry *)
+  input        CI,
   input        CYINIT,
   input  [3:0] DI, S
 );
@@ -219,7 +236,7 @@ endmodule
 
 `endif
 
-module FDRE (output reg Q, input C, CE, D, R);
+module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -231,7 +248,7 @@ module FDRE (output reg Q, input C, CE, D, R);
   endcase endgenerate
 endmodule
 
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -243,7 +260,7 @@ module FDSE (output reg Q, input C, CE, D, S);
   endcase endgenerate
 endmodule
 
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -257,7 +274,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   endcase endgenerate
 endmodule
 
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -271,25 +288,25 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   endcase endgenerate
 endmodule
 
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
@@ -298,9 +315,12 @@ endmodule
 (* abc_box_id = 5 *)
 module RAM32X1D (
   output DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input  D,
+  (* clkbuf_sink *)
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -318,9 +338,12 @@ endmodule
 (* abc_box_id = 6 *)
 module RAM64X1D (
   output DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input  D,
+  (* clkbuf_sink *)
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
@@ -338,9 +361,12 @@ endmodule
 (* abc_box_id = 7 *)
 module RAM128X1D (
   output       DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input        D,
+  (* clkbuf_sink *)
   input        WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input        WE,
   input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;
@@ -354,19 +380,45 @@ endmodule
 
 module SRL16E (
   output Q,
-  input A0, A1, A2, A3, CE, CLK, D
+  input A0, A1, A2, A3, CE,
+  (* clkbuf_sink *)
+  input CLK,
+  input D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+  reg [15:0] r = INIT;
+  assign Q = r[{A3,A2,A1,A0}];
+  generate
+    if (IS_CLK_INVERTED) begin
+      always @(negedge CLK) if (CE) r <= { r[14:0], D };
+    end
+    else
+      always @(posedge CLK) if (CE) r <= { r[14:0], D };
+  endgenerate
+endmodule
+
+module SRLC16E (
+  output Q,
+  output Q15,
+  input A0, A1, A2, A3, CE,
+  (* clkbuf_sink *)
+  input CLK,
+  input D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 
   reg [15:0] r = INIT;
+  assign Q15 = r[15];
   assign Q = r[{A3,A2,A1,A0}];
   generate
     if (IS_CLK_INVERTED) begin
       always @(negedge CLK) if (CE) r <= { r[14:0], D };
     end
     else
-        always @(posedge CLK) if (CE) r <= { r[14:0], D };
+      always @(posedge CLK) if (CE) r <= { r[14:0], D };
   endgenerate
 endmodule
 
@@ -374,7 +426,10 @@ module SRLC32E (
   output Q,
   output Q31,
   input [4:0] A,
-  input CE, CLK, D
+  input CE,
+  (* clkbuf_sink *)
+  input CLK,
+  input D
 );
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -425,7 +480,7 @@ module DSP48E1 (
     input CEINMODE,
     input CEM,
     input CEP,
-    input CLK,
+    (* clkbuf_sink *) input CLK,
     input [24:0] D,
     input [4:0] INMODE,
     input MULTSIGNIN,
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
new file mode 100644
index 000000000..dd4e300ae
--- /dev/null
+++ b/techlibs/xilinx/cells_xtra.py
@@ -0,0 +1,257 @@
+#!/usr/bin/env python3
+
+from argparse import ArgumentParser
+from io import StringIO
+from enum import Enum, auto
+import os.path
+import sys
+
+
+class Cell:
+    def __init__(self, name, keep=False, port_attrs={}):
+        self.name = name
+        self.keep = keep
+        self.port_attrs = port_attrs
+
+
+CELLS = [
+    # Design elements types listed in Xilinx UG953
+    Cell('BSCANE2', keep=True),
+    # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+    #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
+    Cell('CAPTUREE2', keep=True),
+    # Cell('CARRY4'),
+    Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('DCIRESET', keep=True),
+    Cell('DNA_PORT'),
+    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('EFUSE_USR'),
+    # Cell('FDCE'),
+    # Cell('FDPE'),
+    # Cell('FDRE'),
+    # Cell('FDSE'),
+    Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('FRAME_ECCE2'),
+    Cell('GTHE2_CHANNEL'),
+    Cell('GTHE2_COMMON'),
+    Cell('GTPE2_CHANNEL'),
+    Cell('GTPE2_COMMON'),
+    Cell('GTXE2_CHANNEL'),
+    Cell('GTXE2_COMMON'),
+    # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+    Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+    Cell('ICAPE2', keep=True),
+    Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+    Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+    Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+    Cell('ISERDESE2', port_attrs={
+        'CLK': ['clkbuf_sink'],
+        'CLKB': ['clkbuf_sink'],
+        'OCLK': ['clkbuf_sink'],
+        'OCLKB': ['clkbuf_sink'],
+        'CLKDIV': ['clkbuf_sink'],
+        'CLKDIVP': ['clkbuf_sink'],
+    }),
+    Cell('KEEPER'),
+    Cell('LDCE'),
+    Cell('LDPE'),
+    # Cell('LUT1'),
+    # Cell('LUT2'),
+    # Cell('LUT3'),
+    # Cell('LUT4'),
+    # Cell('LUT5'),
+    # Cell('LUT6'),
+    #Cell('LUT6_2'),
+    Cell('MMCME2_ADV'),
+    Cell('MMCME2_BASE'),
+    # Cell('MUXF7'),
+    # Cell('MUXF8'),
+    # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+    Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+    Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
+    Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+    Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+    Cell('PHASER_IN'),
+    Cell('PHASER_IN_PHY'),
+    Cell('PHASER_OUT'),
+    Cell('PHASER_OUT_PHY'),
+    Cell('PHASER_REF'),
+    Cell('PHY_CONTROL'),
+    Cell('PLLE2_ADV'),
+    Cell('PLLE2_BASE'),
+    Cell('PS7', keep=True),
+    Cell('PULLDOWN'),
+    Cell('PULLUP'),
+    #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+    #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+    Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+    # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+    Cell('ROM128X1'),
+    Cell('ROM256X1'),
+    Cell('ROM32X1'),
+    Cell('ROM64X1'),
+    #Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+    #Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+    Cell('STARTUPE2', keep=True),
+    Cell('USR_ACCESSE2'),
+    Cell('XADC'),
+]
+
+class State(Enum):
+    OUTSIDE = auto()
+    IN_MODULE = auto()
+    IN_OTHER_MODULE = auto()
+    IN_FUNCTION = auto()
+    IN_TASK = auto()
+
+def xtract_cell_decl(cell, dirs, outf):
+    for dir in dirs:
+        fname = os.path.join(dir, cell.name + '.v')
+        try:
+            with open(fname) as f:
+                state = State.OUTSIDE
+                found = False
+                # Probably the most horrible Verilog "parser" ever written.
+                for l in f:
+                    l = l.partition('//')[0]
+                    l = l.strip()
+                    if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
+                        if found:
+                            print('Multiple modules in {}.'.format(fname))
+                            sys.exit(1)
+                        elif state != State.OUTSIDE:
+                            print('Nested modules in {}.'.format(fname))
+                            sys.exit(1)
+                        found = True
+                        state = State.IN_MODULE
+                        if cell.keep:
+                            outf.write('(* keep *)\n')
+                        outf.write('module {} (...);\n'.format(cell.name))
+                    elif l.startswith('module '):
+                        if state != State.OUTSIDE:
+                            print('Nested modules in {}.'.format(fname))
+                            sys.exit(1)
+                        state = State.IN_OTHER_MODULE
+                    elif l.startswith('task '):
+                        if state == State.IN_MODULE:
+                            state = State.IN_TASK
+                    elif l.startswith('function '):
+                        if state == State.IN_MODULE:
+                            state = State.IN_FUNCTION
+                    elif l == 'endtask':
+                        if state == State.IN_TASK:
+                            state = State.IN_MODULE
+                    elif l == 'endfunction':
+                        if state == State.IN_FUNCTION:
+                            state = State.IN_MODULE
+                    elif l == 'endmodule':
+                        if state == State.IN_MODULE:
+                            outf.write(l + '\n')
+                            outf.write('\n')
+                        elif state != State.IN_OTHER_MODULE:
+                            print('endmodule in weird place in {}.'.format(cell.name, fname))
+                            sys.exit(1)
+                        state = State.OUTSIDE
+                    elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
+                        if l.endswith((';', ',')):
+                            l = l[:-1]
+                        if ';' in l:
+                            print('Weird port line in {} [{}].'.format(fname, l))
+                            sys.exit(1)
+                        kind, _, ports = l.partition(' ')
+                        for port in ports.split(','):
+                            port = port.strip()
+                            for attr in cell.port_attrs.get(port, []):
+                                outf.write('    (* {} *)\n'.format(attr))
+                            outf.write('    {} {};\n'.format(kind, port))
+                    elif l.startswith('parameter ') and state == State.IN_MODULE:
+                        if 'UNPLACED' in l:
+                            continue
+                        if l.endswith((';', ',')):
+                            l = l[:-1]
+                        while '  ' in l:
+                            l = l.replace('  ', ' ')
+                        if ';' in l:
+                            print('Weird parameter line in {} [{}].'.format(fname, l))
+                            sys.exit(1)
+                        outf.write('    {};\n'.format(l))
+                if state != State.OUTSIDE:
+                    print('endmodule not found in {}.'.format(fname))
+                    sys.exit(1)
+                if not found:
+                    print('Cannot find module {} in {}.'.format(cell.name, fname))
+                    sys.exit(1)
+            return
+        except FileNotFoundError:
+            continue
+    print('Cannot find {}.'.format(cell.name))
+    sys.exit(1)
+
+if __name__ == '__main__':
+    parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from Vivado.')
+    parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
+    args = parser.parse_args()
+
+    dirs = [
+        os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
+        os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
+    ]
+    for dir in dirs:
+        if not os.path.isdir(dir):
+            print('{} is not a directory'.format(dir))
+
+    out = StringIO()
+    for cell in CELLS:
+        xtract_cell_decl(cell, dirs, out)
+
+    with open('cells_xtra.v', 'w') as f:
+        f.write('// Created by cells_xtra.py from Xilinx models\n')
+        f.write('\n')
+        f.write(out.getvalue())
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
deleted file mode 100644
index 53b528820..000000000
--- a/techlibs/xilinx/cells_xtra.sh
+++ /dev/null
@@ -1,147 +0,0 @@
-#!/bin/bash
-
-set -e
-libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
-
-function xtract_cell_decl()
-{
-	for dir in $libdir/xeclib $libdir/retarget; do
-		[ -f $dir/$1.v ] || continue
-		[ -z "$2" ] || echo $2
-		egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
-			sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
-			         s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
-			         s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
-				 s/^ ((end)?module)/\1/; s/^ /    /; /module.*_bb/,/endmodule/ d;'
-		echo; return
-	done
-	echo "Can't find $1."
-	exit 1
-}
-
-{
-	echo "// Created by cells_xtra.sh from Xilinx models"
-	echo
-
-	# Design elements types listed in Xilinx UG953
-	xtract_cell_decl BSCANE2
-	# xtract_cell_decl BUFG
-	xtract_cell_decl BUFGCE
-	xtract_cell_decl BUFGCE_1
-	#xtract_cell_decl BUFGCTRL
-	xtract_cell_decl BUFGMUX
-	xtract_cell_decl BUFGMUX_1
-	xtract_cell_decl BUFGMUX_CTRL
-	xtract_cell_decl BUFH
-	#xtract_cell_decl BUFHCE
-	xtract_cell_decl BUFIO
-	xtract_cell_decl BUFMR
-	xtract_cell_decl BUFMRCE
-	xtract_cell_decl BUFR
-	xtract_cell_decl CAPTUREE2 "(* keep *)"
-	# xtract_cell_decl CARRY4
-	xtract_cell_decl CFGLUT5
-	xtract_cell_decl DCIRESET "(* keep *)"
-	xtract_cell_decl DNA_PORT
-	xtract_cell_decl DSP48E1
-	xtract_cell_decl EFUSE_USR
-	# xtract_cell_decl FDCE
-	# xtract_cell_decl FDPE
-	# xtract_cell_decl FDRE
-	# xtract_cell_decl FDSE
-	xtract_cell_decl FIFO18E1
-	xtract_cell_decl FIFO36E1
-	xtract_cell_decl FRAME_ECCE2
-	xtract_cell_decl GTHE2_CHANNEL
-	xtract_cell_decl GTHE2_COMMON
-	xtract_cell_decl GTPE2_CHANNEL
-	xtract_cell_decl GTPE2_COMMON
-	xtract_cell_decl GTXE2_CHANNEL
-	xtract_cell_decl GTXE2_COMMON
-	# xtract_cell_decl IBUF
-	xtract_cell_decl IBUF_IBUFDISABLE
-	xtract_cell_decl IBUF_INTERMDISABLE
-	xtract_cell_decl IBUFDS
-	xtract_cell_decl IBUFDS_DIFF_OUT
-	xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE
-	xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE
-	xtract_cell_decl IBUFDS_GTE2
-	xtract_cell_decl IBUFDS_IBUFDISABLE
-	xtract_cell_decl IBUFDS_INTERMDISABLE
-	xtract_cell_decl ICAPE2 "(* keep *)"
-	xtract_cell_decl IDDR
-	xtract_cell_decl IDDR_2CLK
-	xtract_cell_decl IDELAYCTRL "(* keep *)"
-	xtract_cell_decl IDELAYE2
-	xtract_cell_decl IN_FIFO
-	xtract_cell_decl IOBUF
-	xtract_cell_decl IOBUF_DCIEN
-	xtract_cell_decl IOBUF_INTERMDISABLE
-	xtract_cell_decl IOBUFDS
-	xtract_cell_decl IOBUFDS_DCIEN
-	xtract_cell_decl IOBUFDS_DIFF_OUT
-	xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN
-	xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE
-	xtract_cell_decl ISERDESE2
-	xtract_cell_decl KEEPER
-	xtract_cell_decl LDCE
-	xtract_cell_decl LDPE
-	# xtract_cell_decl LUT1
-	# xtract_cell_decl LUT2
-	# xtract_cell_decl LUT3
-	# xtract_cell_decl LUT4
-	# xtract_cell_decl LUT5
-	# xtract_cell_decl LUT6
-	#xtract_cell_decl LUT6_2
-	xtract_cell_decl MMCME2_ADV
-	xtract_cell_decl MMCME2_BASE
-	# xtract_cell_decl MUXF7
-	# xtract_cell_decl MUXF8
-	# xtract_cell_decl OBUF
-	xtract_cell_decl OBUFDS
-	xtract_cell_decl OBUFT
-	xtract_cell_decl OBUFTDS
-	xtract_cell_decl ODDR
-	xtract_cell_decl ODELAYE2
-	xtract_cell_decl OSERDESE2
-	xtract_cell_decl OUT_FIFO
-	xtract_cell_decl PHASER_IN
-	xtract_cell_decl PHASER_IN_PHY
-	xtract_cell_decl PHASER_OUT
-	xtract_cell_decl PHASER_OUT_PHY
-	xtract_cell_decl PHASER_REF
-	xtract_cell_decl PHY_CONTROL
-	xtract_cell_decl PLLE2_ADV
-	xtract_cell_decl PLLE2_BASE
-	xtract_cell_decl PS7 "(* keep *)"
-	xtract_cell_decl PULLDOWN
-	xtract_cell_decl PULLUP
-	#xtract_cell_decl RAM128X1D
-	xtract_cell_decl RAM128X1S
-	xtract_cell_decl RAM256X1S
-	xtract_cell_decl RAM32M
-	#xtract_cell_decl RAM32X1D
-	xtract_cell_decl RAM32X1S
-	xtract_cell_decl RAM32X1S_1
-	xtract_cell_decl RAM32X2S
-	xtract_cell_decl RAM64M
-	#xtract_cell_decl RAM64X1D
-	xtract_cell_decl RAM64X1S
-	xtract_cell_decl RAM64X1S_1
-	xtract_cell_decl RAM64X2S
-	# xtract_cell_decl RAMB18E1
-	# xtract_cell_decl RAMB36E1
-	xtract_cell_decl ROM128X1
-	xtract_cell_decl ROM256X1
-	xtract_cell_decl ROM32X1
-	xtract_cell_decl ROM64X1
-	#xtract_cell_decl SRL16E
-	#xtract_cell_decl SRLC32E
-	xtract_cell_decl STARTUPE2 "(* keep *)"
-	xtract_cell_decl USR_ACCESSE2
-	xtract_cell_decl XADC
-} > cells_xtra.new
-
-mv cells_xtra.new cells_xtra.v
-exit 0
-
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index d79349225..b8abdda64 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -1,5 +1,6 @@
-// Created by cells_xtra.sh from Xilinx models
+// Created by cells_xtra.py from Xilinx models
 
+(* keep *)
 module BSCANE2 (...);
     parameter DISABLE_JTAG = "FALSE";
     parameter integer JTAG_CHAIN = 1;
@@ -20,29 +21,39 @@ module BUFGCE (...);
     parameter CE_TYPE = "SYNC";
     parameter [0:0] IS_CE_INVERTED = 1'b0;
     parameter [0:0] IS_I_INVERTED = 1'b0;
+    (* clkbuf_driver *)
     output O;
     input CE;
     input I;
 endmodule
 
 module BUFGCE_1 (...);
+    (* clkbuf_driver *)
     output O;
-    input CE, I;
+    input CE;
+    input I;
 endmodule
 
 module BUFGMUX (...);
     parameter CLK_SEL_TYPE = "SYNC";
+    (* clkbuf_driver *)
     output O;
-    input I0, I1, S;
+    input I0;
+    input I1;
+    input S;
 endmodule
 
 module BUFGMUX_1 (...);
     parameter CLK_SEL_TYPE = "SYNC";
+    (* clkbuf_driver *)
     output O;
-    input I0, I1, S;
+    input I0;
+    input I1;
+    input S;
 endmodule
 
 module BUFGMUX_CTRL (...);
+    (* clkbuf_driver *)
     output O;
     input I0;
     input I1;
@@ -50,16 +61,19 @@ module BUFGMUX_CTRL (...);
 endmodule
 
 module BUFH (...);
+    (* clkbuf_driver *)
     output O;
     input I;
 endmodule
 
 module BUFIO (...);
+    (* clkbuf_driver *)
     output O;
     input I;
 endmodule
 
 module BUFMR (...);
+    (* clkbuf_driver *)
     output O;
     input I;
 endmodule
@@ -68,12 +82,14 @@ module BUFMRCE (...);
     parameter CE_TYPE = "SYNC";
     parameter integer INIT_OUT = 0;
     parameter [0:0] IS_CE_INVERTED = 1'b0;
+    (* clkbuf_driver *)
     output O;
     input CE;
     input I;
 endmodule
 
 module BUFR (...);
+    (* clkbuf_driver *)
     output O;
     input CE;
     input CLR;
@@ -95,8 +111,15 @@ module CFGLUT5 (...);
     output CDO;
     output O5;
     output O6;
-    input I4, I3, I2, I1, I0;
-    input CDI, CE, CLK;
+    input I4;
+    input I3;
+    input I2;
+    input I1;
+    input I0;
+    input CDI;
+    input CE;
+    (* clkbuf_sink *)
+    input CLK;
 endmodule
 
 (* keep *)
@@ -108,7 +131,10 @@ endmodule
 module DNA_PORT (...);
     parameter [56:0] SIM_DNA_VALUE = 57'h0;
     output DOUT;
-    input CLK, DIN, READ, SHIFT;
+    input CLK;
+    input DIN;
+    input READ;
+    input SHIFT;
 endmodule
 
 module EFUSE_USR (...);
@@ -145,11 +171,13 @@ module FIFO18E1 (...);
     output WRERR;
     input [31:0] DI;
     input [3:0] DIP;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input REGCE;
     input RST;
     input RSTREG;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
 endmodule
@@ -190,11 +218,13 @@ module FIFO36E1 (...);
     input [7:0] DIP;
     input INJECTDBITERR;
     input INJECTSBITERR;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input REGCE;
     input RST;
     input RSTREG;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
 endmodule
@@ -1887,6 +1917,7 @@ module IBUF_IBUFDISABLE (...);
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
     input IBUFDISABLE;
 endmodule
@@ -1897,6 +1928,7 @@ module IBUF_INTERMDISABLE (...);
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
     input IBUFDISABLE;
     input INTERMDISABLE;
@@ -1911,7 +1943,10 @@ module IBUFDS (...);
     parameter IFD_DELAY_VALUE = "AUTO";
     parameter IOSTANDARD = "DEFAULT";
     output O;
-    input I, IB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
 endmodule
 
 module IBUFDS_DIFF_OUT (...);
@@ -1919,8 +1954,12 @@ module IBUFDS_DIFF_OUT (...);
     parameter DQS_BIAS = "FALSE";
     parameter IBUF_LOW_PWR = "TRUE";
     parameter IOSTANDARD = "DEFAULT";
-    output O, OB;
-    input I, IB;
+    output O;
+    output OB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
 endmodule
 
 module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
@@ -1932,7 +1971,9 @@ module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
 endmodule
@@ -1946,7 +1987,9 @@ module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
     input INTERMDISABLE;
@@ -1959,7 +2002,9 @@ module IBUFDS_GTE2 (...);
     output O;
     output ODIV2;
     input CEB;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
 endmodule
 
@@ -1971,7 +2016,9 @@ module IBUFDS_IBUFDISABLE (...);
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
 endmodule
@@ -1984,12 +2031,50 @@ module IBUFDS_INTERMDISABLE (...);
     parameter SIM_DEVICE = "7SERIES";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     input I;
+    (* iopad_external_pin *)
     input IB;
     input IBUFDISABLE;
     input INTERMDISABLE;
 endmodule
 
+module IBUFG (...);
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IOSTANDARD = "DEFAULT";
+    output O;
+    (* iopad_external_pin *)
+    input I;
+endmodule
+
+module IBUFGDS (...);
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter DIFF_TERM = "FALSE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IOSTANDARD = "DEFAULT";
+    output O;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
+endmodule
+
+module IBUFGDS_DIFF_OUT (...);
+    parameter DIFF_TERM = "FALSE";
+    parameter DQS_BIAS = "FALSE";
+    parameter IBUF_LOW_PWR = "TRUE";
+    parameter IOSTANDARD = "DEFAULT";
+    output O;
+    output OB;
+    (* iopad_external_pin *)
+    input I;
+    (* iopad_external_pin *)
+    input IB;
+endmodule
+
 (* keep *)
 module ICAPE2 (...);
     parameter [31:0] DEVICE_ID = 32'h04244093;
@@ -2013,6 +2098,7 @@ module IDDR (...);
     parameter XON = "TRUE";
     output Q1;
     output Q2;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input D;
@@ -2030,7 +2116,9 @@ module IDDR_2CLK (...);
     parameter SRTYPE = "SYNC";
     output Q1;
     output Q2;
+    (* clkbuf_sink *)
     input C;
+    (* clkbuf_sink *)
     input CB;
     input CE;
     input D;
@@ -2042,6 +2130,7 @@ endmodule
 module IDELAYCTRL (...);
     parameter SIM_DEVICE = "7SERIES";
     output RDY;
+    (* clkbuf_sink *)
     input REFCLK;
     input RST;
 endmodule
@@ -2061,6 +2150,7 @@ module IDELAYE2 (...);
     parameter integer SIM_DELAY_D = 0;
     output [4:0] CNTVALUEOUT;
     output DATAOUT;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input CINVCTRL;
@@ -2092,9 +2182,11 @@ module IN_FIFO (...);
     output [7:0] Q7;
     output [7:0] Q8;
     output [7:0] Q9;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input RESET;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
     input [3:0] D0;
@@ -2115,8 +2207,10 @@ module IOBUF (...);
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
+    (* iopad_external_pin *)
     inout IO;
-    input I, T;
+    input I;
+    input T;
 endmodule
 
 module IOBUF_DCIEN (...);
@@ -2127,6 +2221,7 @@ module IOBUF_DCIEN (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     inout IO;
     input DCITERMDISABLE;
     input I;
@@ -2142,6 +2237,7 @@ module IOBUF_INTERMDISABLE (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     inout IO;
     input I;
     input IBUFDISABLE;
@@ -2156,8 +2252,11 @@ module IOBUFDS (...);
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
-    inout IO, IOB;
-    input I, T;
+    (* iopad_external_pin *)
+    inout IO;
+    inout IOB;
+    input I;
+    input T;
 endmodule
 
 module IOBUFDS_DCIEN (...);
@@ -2169,7 +2268,9 @@ module IOBUFDS_DCIEN (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input DCITERMDISABLE;
     input I;
@@ -2184,7 +2285,9 @@ module IOBUFDS_DIFF_OUT (...);
     parameter IOSTANDARD = "DEFAULT";
     output O;
     output OB;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input I;
     input TM;
@@ -2200,7 +2303,9 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input DCITERMDISABLE;
     input I;
@@ -2218,7 +2323,9 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    (* iopad_external_pin *)
     inout IO;
+    (* iopad_external_pin *)
     inout IOB;
     input I;
     input IBUFDISABLE;
@@ -2266,15 +2373,21 @@ module ISERDESE2 (...);
     input BITSLIP;
     input CE1;
     input CE2;
+    (* clkbuf_sink *)
     input CLK;
+    (* clkbuf_sink *)
     input CLKB;
+    (* clkbuf_sink *)
     input CLKDIV;
+    (* clkbuf_sink *)
     input CLKDIVP;
     input D;
     input DDLY;
     input DYNCLKDIVSEL;
     input DYNCLKSEL;
+    (* clkbuf_sink *)
     input OCLK;
+    (* clkbuf_sink *)
     input OCLKB;
     input OFB;
     input RST;
@@ -2293,7 +2406,10 @@ module LDCE (...);
     parameter MSGON = "TRUE";
     parameter XON = "TRUE";
     output Q;
-    input CLR, D, G, GE;
+    input CLR;
+    input D;
+    input G;
+    input GE;
 endmodule
 
 module LDPE (...);
@@ -2303,7 +2419,10 @@ module LDPE (...);
     parameter MSGON = "TRUE";
     parameter XON = "TRUE";
     output Q;
-    input D, G, GE, PRE;
+    input D;
+    input G;
+    input GE;
+    input PRE;
 endmodule
 
 module MMCME2_ADV (...);
@@ -2451,7 +2570,10 @@ module OBUFDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
-    output O, OB;
+    (* iopad_external_pin *)
+    output O;
+    (* iopad_external_pin *)
+    output OB;
     input I;
 endmodule
 
@@ -2460,20 +2582,27 @@ module OBUFT (...);
     parameter integer DRIVE = 12;
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
+    (* iopad_external_pin *)
     output O;
-    input I, T;
+    input I;
+    input T;
 endmodule
 
 module OBUFTDS (...);
     parameter CAPACITANCE = "DONT_CARE";
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
-    output O, OB;
-    input I, T;
+    (* iopad_external_pin *)
+    output O;
+    (* iopad_external_pin *)
+    output OB;
+    input I;
+    input T;
 endmodule
 
 module ODDR (...);
     output Q;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input D1;
@@ -2504,6 +2633,7 @@ module ODELAYE2 (...);
     parameter integer SIM_DELAY_D = 0;
     output [4:0] CNTVALUEOUT;
     output DATAOUT;
+    (* clkbuf_sink *)
     input C;
     input CE;
     input CINVCTRL;
@@ -2549,7 +2679,9 @@ module OSERDESE2 (...);
     output TBYTEOUT;
     output TFB;
     output TQ;
+    (* clkbuf_sink *)
     input CLK;
+    (* clkbuf_sink *)
     input CLKDIV;
     input D1;
     input D2;
@@ -2591,9 +2723,11 @@ module OUT_FIFO (...);
     output [3:0] Q9;
     output [7:0] Q5;
     output [7:0] Q6;
+    (* clkbuf_sink *)
     input RDCLK;
     input RDEN;
     input RESET;
+    (* clkbuf_sink *)
     input WRCLK;
     input WREN;
     input [7:0] D0;
@@ -3577,7 +3711,17 @@ module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module RAM256X1S (...);
@@ -3586,6 +3730,7 @@ module RAM256X1S (...);
     output O;
     input [7:0] A;
     input D;
+    (* clkbuf_sink *)
     input WCLK;
     input WE;
 endmodule
@@ -3608,6 +3753,7 @@ module RAM32M (...);
     input [1:0] DIB;
     input [1:0] DIC;
     input [1:0] DID;
+    (* clkbuf_sink *)
     input WCLK;
     input WE;
 endmodule
@@ -3616,22 +3762,48 @@ module RAM32X1S (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module RAM32X1S_1 (...);
     parameter [31:0] INIT = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module RAM32X2S (...);
     parameter [31:0] INIT_00 = 32'h00000000;
     parameter [31:0] INIT_01 = 32'h00000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output O0, O1;
-    input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
+    output O0;
+    output O1;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input D0;
+    input D1;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module RAM64M (...);
@@ -3652,6 +3824,7 @@ module RAM64M (...);
     input DIB;
     input DIC;
     input DID;
+    (* clkbuf_sink *)
     input WCLK;
     input WE;
 endmodule
@@ -3660,46 +3833,97 @@ module RAM64X1S (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module RAM64X1S_1 (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
     output O;
-    input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input D;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module RAM64X2S (...);
     parameter [63:0] INIT_00 = 64'h0000000000000000;
     parameter [63:0] INIT_01 = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output O0, O1;
-    input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;
+    output O0;
+    output O1;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input D0;
+    input D1;
+    (* clkbuf_sink *)
+    input WCLK;
+    input WE;
 endmodule
 
 module ROM128X1 (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     output O;
-    input A0, A1, A2, A3, A4, A5, A6;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
 endmodule
 
 module ROM256X1 (...);
     parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
     output O;
-    input A0, A1, A2, A3, A4, A5, A6, A7;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
+    input A6;
+    input A7;
 endmodule
 
 module ROM32X1 (...);
     parameter [31:0] INIT = 32'h00000000;
     output O;
-    input A0, A1, A2, A3, A4;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
 endmodule
 
 module ROM64X1 (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     output O;
-    input A0, A1, A2, A3, A4, A5;
+    input A0;
+    input A1;
+    input A2;
+    input A3;
+    input A4;
+    input A5;
 endmodule
 
 (* keep *)
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 26d01ce40..5e491b86b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -ise\n");
+		log("        generate an output netlist suitable for ISE (enables -iopad)\n");
+		log("\n");
 		log("    -nobram\n");
 		log("        do not use block RAM cells in output netlist\n");
 		log("\n");
@@ -80,6 +83,14 @@ struct SynthXilinxPass : public ScriptPass
 		log("\n");
 		log("    -nodsp\n");
 		log("        do not use DSP48E1s to implement multipliers and associated logic\n");
+		log("    -iopad\n");
+		log("        enable I/O buffer insertion (selected automatically by -ise)\n");
+		log("\n");
+		log("    -noiopad\n");
+		log("        disable I/O buffer insertion (only useful with -ise)\n");
+		log("\n");
+		log("    -noclkbuf\n");
+		log("        disable automatic clock buffer insertion\n");
 		log("\n");
 		log("    -widemux <int>\n");
 		log("        enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
@@ -107,7 +118,8 @@ struct SynthXilinxPass : public ScriptPass
 	}
 
 	std::string top_opt, edif_file, blif_file, family;
-	bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
+	bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9;
+	bool flatten_before_abc;
 	int widemux;
 
 	void clear_flags() YS_OVERRIDE
@@ -119,6 +131,10 @@ struct SynthXilinxPass : public ScriptPass
 		flatten = false;
 		retime = false;
 		vpr = false;
+		ise = false;
+		iopad = false;
+		noiopad = false;
+		noclkbuf = false;
 		nocarry = false;
 		nobram = false;
 		nolutram = false;
@@ -127,6 +143,7 @@ struct SynthXilinxPass : public ScriptPass
 		nowidelut = false;
 		nodsp = false;
 		abc9 = false;
+		flatten_before_abc = false;
 		widemux = 0;
 	}
 
@@ -166,6 +183,10 @@ struct SynthXilinxPass : public ScriptPass
 				flatten = true;
 				continue;
 			}
+			if (args[argidx] == "-flatten_before_abc") {
+				flatten_before_abc = true;
+				continue;
+			}
 			if (args[argidx] == "-retime") {
 				retime = true;
 				continue;
@@ -182,6 +203,22 @@ struct SynthXilinxPass : public ScriptPass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-ise") {
+				ise = true;
+				continue;
+			}
+			if (args[argidx] == "-iopad") {
+				iopad = true;
+				continue;
+			}
+			if (args[argidx] == "-noiopad") {
+				noiopad = true;
+				continue;
+			}
+			if (args[argidx] == "-noclkbuf") {
+				noclkbuf = true;
+				continue;
+			}
 			if (args[argidx] == "-nocarry") {
 				nocarry = true;
 				continue;
@@ -407,6 +444,8 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("map_luts")) {
 			run("opt_expr -mux_undef");
+			if (flatten_before_abc)
+				run("flatten");
 			if (help_mode)
 				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
 			else if (abc9) {
@@ -435,6 +474,18 @@ struct SynthXilinxPass : public ScriptPass
 			run("clean");
 		}
 
+		if (check_label("finalize")) {
+			bool do_iopad = iopad || (ise && !noiopad);
+			if (help_mode || !noclkbuf) {
+				if (help_mode || do_iopad)
+					run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
+				else
+					run("clkbufmap -buf BUFG O:I");
+			}
+			if (do_iopad)
+				run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
+		}
+
 		if (check_label("check")) {
 			run("hierarchy -check");
 			run("stat -tech xilinx");
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
index eb1a29579..041d6b54f 100644
--- a/techlibs/xilinx/xc6s_brams_bb.v
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -1,5 +1,7 @@
 module RAMB8BWER (
+	(* clkbuf_sink *)
 	input CLKAWRCLK,
+	(* clkbuf_sink *)
 	input CLKBRDCLK,
 	input ENAWREN,
 	input ENBRDEN,
@@ -87,7 +89,9 @@ module RAMB8BWER (
 endmodule
 
 module RAMB16BWER (
+	(* clkbuf_sink *)
 	input CLKA,
+	(* clkbuf_sink *)
 	input CLKB,
 	input ENA,
 	input ENB,
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index a682ba4a7..a43b4b5a1 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -1,5 +1,7 @@
 module RAMB18E1 (
+	(* clkbuf_sink *)
 	input CLKARDCLK,
+	(* clkbuf_sink *)
 	input CLKBWRCLK,
 	input ENARDEN,
 	input ENBWREN,
@@ -123,7 +125,9 @@ module RAMB18E1 (
 endmodule
 
 module RAMB36E1 (
+	(* clkbuf_sink *)
 	input CLKARDCLK,
+	(* clkbuf_sink *)
 	input CLKBWRCLK,
 	input ENARDEN,
 	input ENBWREN,