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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 19:52:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 19:52:54 -0700 |
| commit | 29db96fa1ff89a8224f8ae3c51c754e16a34c31c (patch) | |
| tree | ba93d83860b9749a9e7bc9efa79e8c7a0d9b935a /techlibs/xilinx | |
| parent | 895e2befa76bd326cc47fd40de112ea067fcaf98 (diff) | |
| download | yosys-29db96fa1ff89a8224f8ae3c51c754e16a34c31c.tar.gz yosys-29db96fa1ff89a8224f8ae3c51c754e16a34c31c.tar.bz2 yosys-29db96fa1ff89a8224f8ae3c51c754e16a34c31c.zip | |
Revert "Vivado does not like zero width port connections"
This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98.
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/xilinx_finalise.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/xilinx_finalise.cc b/techlibs/xilinx/xilinx_finalise.cc index 2c0bd3534..db73babe3 100644 --- a/techlibs/xilinx/xilinx_finalise.cc +++ b/techlibs/xilinx/xilinx_finalise.cc @@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass for (auto cell : module->selected_cells()) { if (cell->type != ID(DSP48E1)) continue; - for (auto conn : cell->connections()) { + for (auto &conn : cell->connections_) { if (!cell->output(conn.first)) continue; bool purge = true; @@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass if (purge) { log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); - cell->unsetPort(conn.first); + conn.second = SigSpec(); } } } |