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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2020-02-03 10:56:11 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2020-02-03 10:56:41 -0300 |
| commit | 313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc (patch) | |
| tree | f35f8834f0cc30380c32d5ed3a38cb2673304931 /techlibs/xilinx | |
| parent | 71f3afb9a26e7bad2a9e9d59877a94cbd757cad4 (diff) | |
| parent | 7033503cd9e40e16c11fe6c805a436b0e23989dd (diff) | |
| download | yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.tar.gz yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.tar.bz2 yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 29f6b05cc..faf66bc18 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -153,7 +153,7 @@ endmatch match $__XILINX_RAM32X2Q min bits 5 - min rports 3 + min rports 2 min wports 1 make_outreg or_next_if_better @@ -161,7 +161,7 @@ endmatch match $__XILINX_RAM64X1Q min bits 5 - min rports 3 + min rports 2 min wports 1 make_outreg endmatch |