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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-23 15:58:06 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-23 15:58:06 +0100 |
| commit | 532091afcbb8ba547392f51ba3a020d993e099da (patch) | |
| tree | f8655ebf265301120dd3e8bf43c749f2a80442dd /techlibs/xilinx | |
| parent | 9ab850e45eb907a6778c62eace974221d18b49c2 (diff) | |
| download | yosys-532091afcbb8ba547392f51ba3a020d993e099da.tar.gz yosys-532091afcbb8ba547392f51ba3a020d993e099da.tar.bz2 yosys-532091afcbb8ba547392f51ba3a020d993e099da.zip | |
Added more generic _TECHMAP_ wire mechanism to techmap pass
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells.v b/techlibs/xilinx/cells.v index 8c8b9c759..5bf8ccd86 100644 --- a/techlibs/xilinx/cells.v +++ b/techlibs/xilinx/cells.v @@ -46,7 +46,7 @@ module \$lut (I, O); .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]), .I4(I[4]), .I5(I[5])); end else begin:error - wire TECHMAP_FAIL; + wire _TECHMAP_FAIL_ = 1; end endgenerate |