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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-08-29 21:09:40 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-29 21:09:40 +0300 |
| commit | 5dda8f39a6b13610084d259e5490604380350eba (patch) | |
| tree | 9dd6443a5da1b7a5364c832b0d2cac3ba098c9c3 /techlibs/xilinx | |
| parent | d360693040dda29aba4ef2583e522c6ab88a4961 (diff) | |
| parent | 14677610602ee18bcf1a41a0c54a626965e6bb06 (diff) | |
| download | yosys-5dda8f39a6b13610084d259e5490604380350eba.tar.gz yosys-5dda8f39a6b13610084d259e5490604380350eba.tar.bz2 yosys-5dda8f39a6b13610084d259e5490604380350eba.zip | |
Merge pull request #2 from YosysHQ/master
Pull from upstream
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 973e17212..e12b77c02 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -380,9 +380,10 @@ endmodule module SRL16E ( output Q, + input A0, A1, A2, A3, CE, (* clkbuf_sink *) input CLK, - input A0, A1, A2, A3, CE, D + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -401,7 +402,10 @@ endmodule module SRLC16E ( output Q, output Q15, - input A0, A1, A2, A3, CE, CLK, D + input A0, A1, A2, A3, CE, + (* clkbuf_sink *) + input CLK, + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -422,9 +426,10 @@ module SRLC32E ( output Q, output Q31, input [4:0] A, + input CE, (* clkbuf_sink *) input CLK, - input CE, D + input D ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; |