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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-05 06:49:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-05 06:49:36 -0700 |
| commit | 5fa06e4894f13d82cf847f8d7b078c5b46a01737 (patch) | |
| tree | 03167c4eff66112816defadc9bda3a766cab587d /techlibs/xilinx | |
| parent | 7a62ee57b4953a01637086d409a99b9779a7d6c9 (diff) | |
| parent | e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3 (diff) | |
| download | yosys-5fa06e4894f13d82cf847f8d7b078c5b46a01737.tar.gz yosys-5fa06e4894f13d82cf847f8d7b078c5b46a01737.tar.bz2 yosys-5fa06e4894f13d82cf847f8d7b078c5b46a01737.zip | |
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1c190d37e..229ffcb3d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -619,11 +619,13 @@ struct SynthXilinxPass : public ScriptPass run("techmap " + techmap_args); run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v"); std::string abc9_opts; - auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); - if (active_design->scratchpad.count(k)) + std::string k = "synth_xilinx.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); - else + else { + k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str()); + } if (nowidelut) abc9_opts += stringf(" -maxlut %d", lut_size); if (dff_mode) |