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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-24 14:09:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-24 14:09:15 -0700 |
| commit | 60af2ca94de482f09aaaa7d6eed66c299248f8f1 (patch) | |
| tree | c7c12d602a815668bd11d78da2ddac3258c459a8 /techlibs/xilinx | |
| parent | 52e9036d393837a12bd1daca22d197acd1d91a73 (diff) | |
| download | yosys-60af2ca94de482f09aaaa7d6eed66c299248f8f1.tar.gz yosys-60af2ca94de482f09aaaa7d6eed66c299248f8f1.tar.bz2 yosys-60af2ca94de482f09aaaa7d6eed66c299248f8f1.zip | |
Transpose CARRY4 delays
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc.box | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 92ea5537b..9653fe5b8 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -15,16 +15,14 @@ MUXF8 2 1 3 1 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 CARRY4 3 1 10 8 -271 157 228 114 222 334 239 313 -536 494 592 580 482 598 584 642 -379 465 540 526 - 407 556 615 -- 445 520 507 - - 537 596 -- - 356 398 - - - 438 -- - - 385 - - - - -340 433 512 508 223 400 523 582 -- 469 548 528 - 205 558 618 -- - 292 376 - - 226 330 -- - - 380 - - - 227 +271 536 379 - - - 340 - - - +157 494 465 445 - - 433 469 - - +228 592 540 520 356 - 512 548 292 - +114 580 526 507 398 385 508 528 378 380 +222 482 - - - - 223 - - - +334 598 407 - - - 400 205 - - +239 584 556 537 - - 523 558 226 - +313 642 615 596 438 - 582 618 330 227 # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE |