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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:37:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:37:32 -0700 |
| commit | 6e475484b262a93562560e5f4558483558777e76 (patch) | |
| tree | 170dcde36a29e7d5873f5ffcdc257e40facb23c6 /techlibs/xilinx | |
| parent | 4eb5847dbdbb4a4efcde20aa81455eed8196db56 (diff) | |
| parent | a94a8f3e4030b3a4697c2201ef65c83b01f25ffb (diff) | |
| download | yosys-6e475484b262a93562560e5f4558483558777e76.tar.gz yosys-6e475484b262a93562560e5f4558483558777e76.tar.bz2 yosys-6e475484b262a93562560e5f4558483558777e76.zip | |
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 973e17212..e12b77c02 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -380,9 +380,10 @@ endmodule module SRL16E ( output Q, + input A0, A1, A2, A3, CE, (* clkbuf_sink *) input CLK, - input A0, A1, A2, A3, CE, D + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -401,7 +402,10 @@ endmodule module SRLC16E ( output Q, output Q15, - input A0, A1, A2, A3, CE, CLK, D + input A0, A1, A2, A3, CE, + (* clkbuf_sink *) + input CLK, + input D ); parameter [15:0] INIT = 16'h0000; parameter [0:0] IS_CLK_INVERTED = 1'b0; @@ -422,9 +426,10 @@ module SRLC32E ( output Q, output Q31, input [4:0] A, + input CE, (* clkbuf_sink *) input CLK, - input CE, D + input D ); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_CLK_INVERTED = 1'b0; |